FIG. 1 schematically illustrates an integrated circuit IC having a structure of the triple well type, making it possible to insulate a well 1, here of P type conductivity, from the rest of the semiconductor substrate SB, which is also of P type conductivity.
More precisely, the well 1 is insulated from the substrate SB by an insulating region having a first insulating trench 2 (for example, of the type known by the person skilled in the art by the acronym STI: shallow trench isolation) extending into the substrate from a first face FS of the substrate and surrounding the well 1.
The insulating region also has a semiconductor layer 3 of N type conductivity buried in the substrate below the well 1.
Lastly, the insulating region comprises an intermediate insulating zone ensuring electrical insulation continuity between the first insulating trench 2 and the buried semiconductor layer 3.
Here, this intermediate insulating zone has a well 4 laterally surrounding the well 1 and extending between the first insulating trench 2 and the buried semiconductor layer 3. This well 4 is produced by implantation of dopants of N type conductivity.
Such an insulating region based on implanted wells 4 requires that a certain distance be maintained between the edge of the insulating trench 2 and the edge of the well 4 so as to prevent any risk of overflow of N dopants into the P well by a diffusion phenomenon, the effect of which would be to reduce the effective size of the P well.
However, this dimensional constraint presents a surface cost which leads to an increase in the surface area of the wells.
These wells may furthermore be used in order to form therein decoupling capacitors connected between the supply voltage and the ground. These decoupling capacitors contain, for example, one or more lines of polysilicon insulated from the P well by an insulating material such as a silicon oxide. However, it is found that such decoupling capacitors have non-negligible leakage currents and a capacitive value which may in certain cases be relatively low.
There is a need in the art to reduce the surface occupancy of a semiconductor well insulated by a structure of the triple well type, while further producing in this well decoupling capacitors having a higher capacitance value and reduced leakage currents.